1. Field of the Invention
The present invention generally relates to digital flip-flop circuits and more specifically to a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations.
2. Description of the Related Art
Power dissipation is a significant problem in conventional integrated circuits. A large fraction of the power dissipated in conventional digital integrated circuits is consumed in the clock network. The amount of energy that is consumed by flip-flops due to data transitions is small because the activity factor, the fraction of time the data input of the flip-flop toggles, is quite low, typically about 5-10%. In contrast, the clock input load and clock energy is an increasingly important metric to consider when determining the energy that is consumed by the latches and flip-flops in a conventional integrated circuit. Reducing the clock-switched capacitance by a given amount produces 10× the power savings compared with reducing the data-switched capacitance by the same amount.
FIG. 1 illustrates a conventional flip-flop circuit 100. The flip-flop circuit 100 includes 26 transistors, including the inverters used to generate clkN and clkP. Each of the clock signals, clkP has a load of four transistor devices and clkN ha a load of six transistor devices. At each clock transition, 12 transistor gates (and corresponding wires) toggle, including the gates coupled to the clk signal.
FIG. 2 illustrates another conventional flip-flop circuit 200 that is sometimes referred to as the StrongARM flip-flop. Compared with the flip-flop circuit 100, the total clock load presented to Clk 220 of the flip-flop circuit 200 is only three transistor devices. The total number of transistors in the flip-flop circuit 200 is twenty, where each NAND gate includes four transistors. However, half of the internal nodes toggle each clock cycle. The internal nodes include the gates that are coupled to Clk 220 and the node 210. The node 210 is coupled to four transistor gates and three transistor sources or drains. The total number of internal nodes that toggle each clock cycle is seven gates and ten transistor sources or drains or the equivalent of approximately seventeen gate loads. Suppose input d is high and all of the internal nodes are initially high (Vdd or a Vt drop below Vdd). When the Clk 220 goes high both source and drain of input transistor 201 go low, both source and drain of the transistor 202 go low, the drain of transistor 203 goes low, both sides of bridging transistor 204 go low, both the source and drain of input transistor 205 go low, and the source of transistor 206 goes low.
Accordingly, what is needed in the art is a flip-flop circuit that reduces the energy consumed by reducing the number of internal nodes that toggle during a clock cycle. Additionally, the flip-flop circuit should function independent of fabrication process variations by not relying on sizing relationships between different transistors in the flip-flop circuit.